Delay locked loops (DLLs) are widely employed in microprocessors, memory, and communication integrated circuits to reduce chip clock buffering delays and improve input-output timing margins. DLLs can include a voltage-controlled delay line (VCDL), a phase detector and a charge pump. DLLs can function to achieve phase alignment between an input clock and an output clock from a final stage of the VCDL. After the phase alignment is achieved, each VCDL delay stage can provide a stable clock signal which is phase shifted from an input clock in the phase detector.
In a DLL, an input clock signal can propagate through the VCDL and develop phase shift (or time delay) at each delay stage of the VCDL. The phase shift of each delay stage can be controlled by a voltage of a loop filter. An output can be taken from one of the delay stages. A phase of an output signal can be compared with a phase of the input clock in the phase detector. The phase detector can generate phase error information, which can be transferred to the charge pump. The charge pump can use the phase error information to adjust the voltage of the loop filter, and thus to change the phase shift (or time delay) of the VCDL. A phase shift (or time delay) error can be gradually reduced to zero. At that time, the phase shift (or time delay) of the whole VCDL line can become equal to one clock period and the voltage of the loop filter can be stabilized, which can indicate that a locked state has been established.
Reference will now be made to the embodiments illustrated, and specific language will be used herein to describe the same. It will nevertheless be understood that no limitation on invention scope is thereby intended.